The simulation process is carried out by tanner toolv14.11 to check the functionality of the PASTA circuits. From the results, the proposed GDL logic based PASTA offers less number of transistors (area) and low power consumption than the existing CSCMOS technique. Comparison between these two techniques is performed to analyze the results. Similarly, the structure of XOR gate and half adder is reduced to achieve the low area and low power. To overcome this problem, the modified gate diffusion input (GDI) logic is used in the proposed parallel asynchronous self time adder (PASTA) technique.
So area and power consumption is very high in existing technique. Also large number of transistor is required to design any logic gate or digital circuits. In the conventional technique, complementary static CMOS (CSCMOS) technology is used to design a parallel self-timed adder circuit, in which the number of NMOS and PMOS are equal. In this paper, the circuit level optimization process is followed to reduce the area and power. We can reduce the power by using either circuit level optimization or logical level optimization. CMOS technology is mainly used in VLSI circuits to reduce the number of transistors and achieve the low power.
